module tb;

reg clk;
reg reset_n;

initial begin
  clk = 1'b0;
  reset_n = 1'b0;
  #100;
  reset_n = 1'b1;
  #5000 $finish;
end

always #5 clk = ~clk;

reg prescalser2;
reg prescalser4;
reg prescalser6;
reg prescalser8;
reg prescalser16;
reg prescalser32;

always @(posedge clk, negedge reset_n) begin
  if(!reset_n)
    prescalser2 <= 0;
  else
    prescalser2 <= ~prescalser2;
end

reg [7:0] cnt;
always @(posedge clk, negedge reset_n) begin
  if(!reset_n)
    cnt <= 8'h0;
  else
    cnt <= cnt+1'b1;
end

always @(posedge clk, negedge reset_n) begin
  if(!reset_n)begin
    prescalser4 <= 1'b0;
    prescalser8 <= 1'b0;
    prescalser16 <= 1'b0;
    prescalser32 <= 1'b0;
  end else begin
    prescalser4 <= cnt[1];
    prescalser8 <= cnt[2];
    prescalser16 <= cnt[3];
    prescalser32 <= cnt[4];
  end
end


wire clk_out;
prescaler2_5 u0_prescaler2_5(
 .clk     (clk),
 .rst_n   (reset_n),
 .clk_out (clk_out)
);

initial begin            
  $dumpfile("wave.vcd"); //生成的vcd文件名称
  $dumpvars(0, tb);      //tb模块名称
end

endmodule
